发明名称 Method and apparatus for treatment of state confidence data retrieved from a non-volatile memory array
摘要 Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.
申请公布号 US9582357(B2) 申请公布日期 2017.02.28
申请号 US201213977012 申请日期 2012.03.29
申请人 INTEL CORPORATION 发明人 Goldman Matthew;Tran Wayne D.;Madraswala Aliasgar S.;Park Sungho
分类号 G11C29/00;G06F11/10;G11C16/26;G11C16/34;G11C11/56;G11C29/04 主分类号 G11C29/00
代理机构 代理人
主权项 1. An apparatus, comprising: a controller to retrieve data from a non-volatile memory; and an error correction module operable on the controller to: read a multiple-bit memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions, the memory read comprising: determining, for a first bit of the multiple-bit memory cell, a set of reference voltages marking a respective set of transitions between logical states; andperforming, for each reference voltage of the set of reference voltages, a set of sensing measurements, the set of sensing measurements for each reference voltage of the set of reference voltages comprising reading the non-volatile memory at multiple sense reference voltages that span a range of threshold voltage about each reference voltage; andset a first set of bits in an encoded output, the first set of bits comprising a logical state bit and one or more additional bits, the logical state bit to indicate a logical state of the memory cell and the one or more additional bits to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than a number of the first set of bits.
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