Three-dimensional semiconductor device and method of manufacturing the same

摘要

A three-dimensional semiconductor device is provided, comprising: a plurality of ground selection line (GSL) sections separately formed on a substrate, the GSL sections being electrically insulated from each other and extended in parallel to each other, and the GSL sections extending along a first direction; a plurality of stacked structures vertically formed on the GSL sections on the substrate, and each stacked structure comprising alternated semiconductor layers and insulating layers; string selection lines (SSLs) separately formed on the stacked structures, and the string selection lines extending along the first direction; and bit lines disposed above the SSLs and extending along a second direction, the bit lines arranged parallel to each other and in perpendicular to the SSLs and GSL sections, wherein a plurality of memory cells of memory layers respectively defined by the stacked structures, the SSLs, the GSL sections and the bit lines correspondingly.

主权项

1. A three-dimensional (3D) semiconductor device, comprising:
a plurality of ground selection line (GSL) sections separately formed on a substrate, the GSL sections being electrically insulated from each other and extended in parallel to each other, and the GSL sections extending along a first direction, wherein the GSL sections comprise a plurality of odd-numbered GSL sections forming a finger structure and a plurality of even-numbered GSL sections forming a finger structure, and the odd-numbered GSL sections are interlaced with the even-numbered GSL sections; a plurality of stacked structures vertically formed on the GSL sections, and each stacked structure comprising alternated semiconductor layers and insulating layers; a plurality of string selection lines (SSLs) separately formed on the stacked structures, and the string selection lines extending along the first direction; and a plurality of bit lines disposed above the SSLs and extending along a second direction, the bit lines arranged parallel to each other and in perpendicular to the SSLs and GSL sections, wherein a plurality of memory cells of memory layers are respectively defined by the stacked structures, the SSLs, the GSL sections and the bit lines correspondingly, and a plurality of memory pages respectively correspond to the memory cells associated with one of the GSL sections.