发明名称 NAND flash memory having multiple cell substrates
摘要 A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
申请公布号 US9583204(B2) 申请公布日期 2017.02.28
申请号 US201514753500 申请日期 2015.06.29
申请人 Conversant Intellectual Property Management Inc. 发明人 Kim Jin-Ki
分类号 G11C11/34;G11C16/34;G11C16/16;H01L27/115 主分类号 G11C11/34
代理机构 Borden Ladner Gervais LLP 代理人 Borden Ladner Gervais LLP ;Hung Shin
主权项 1. A NAND flash memory comprising: at least first and second well sectors, each of the first and second well sectors including at least one memory block; a first bitline segment connected to the at least one memory block of the first well sector; a second bitline segment connected to the at least one memory block of the second well sector; and isolation circuitry connected between the first bitline segment and second bitline segment, the isolation circuitry configured to: i)be turned off during at least one memory operation of a plurality of different possible memory operations performable within the NAND flash memory; andii)be turned on at certain times other than during the at least one memory operation.
地址 Ottawa CA