| 发明名称 | Asymmetric set combined cache | ||
| 摘要 | Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may include one or more processing cores for processing of data, and a cache memory to cache data from a main memory for the one or more processing cores, the cache memory including a first cache portion, the first cache portion including a direct-mapped cache, and a second cache portion, the second cache portion including a multi-way cache. The cache memory includes asymmetric sets in the first cache portion and the second cache portion, the first cache portion being larger than the second cache portion. A coordinated replacement policy for the cache memory provides for replacement of data in the first cache portion and the second cache portion. | ||
| 申请公布号 | US9582430(B2) | 申请公布日期 | 2017.02.28 |
| 申请号 | US201514671927 | 申请日期 | 2015.03.27 |
| 申请人 | Intel Corporation | 发明人 | Greenfield Zvika;Bonen Nadav;Diamand Israel |
| 分类号 | G06F13/00;G06F12/08 | 主分类号 | G06F13/00 |
| 代理机构 | Blakely, Sokoloff, Taylor & Zafman LLP | 代理人 | Blakely, Sokoloff, Taylor & Zafman LLP |
| 主权项 | 1. A processor comprising: one or more processing cores for processing of data; and a cache memory to cache data for the one or more processing cores, wherein the cache memory includes: a first cache portion including a direct-mapped cache, anda second cache portion including a multi-way cache; wherein the cache memory includes asymmetric sets in the first cache portion and the second cache portion, the first cache portion being larger than the second cache portion; and wherein a coordinated replacement policy for the cache memory provides for replacement of data in the first cache portion and the second cache portion. | ||
| 地址 | Santa Clara CA US | ||