发明名称 |
Isolation structure |
摘要 |
A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well. |
申请公布号 |
US9583564(B2) |
申请公布日期 |
2017.02.28 |
申请号 |
US201414177451 |
申请日期 |
2014.02.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Yu Shu-Jenn;Hsieh Meng-Wei;Yang Shih-Hsien;Tseng Hua-Chou;Chao Chih-Ping |
分类号 |
H01L29/78;H01L21/761;H01L29/06;H01L21/762;H01L29/10;H01L29/66 |
主分类号 |
H01L29/78 |
代理机构 |
Hauptman Ham, LLP |
代理人 |
Hauptman Ham, LLP |
主权项 |
1. A structure comprising:
a p-type substrate; a deep n-type well adjacent to the p-type substrate and having a first conductive path to a first terminal; a deep p-type well
in the deep n-type well,the deep p-type well is separated from the p-type substrate by the deep n-type well, andthe deep p-type well has a second conductive path to a second terminal, the second terminal being configured to bias the deep p-type well; a first n-type well over the deep p-type well; a first p-type well over the deep p-type well, wherein the deep p-type well has a third conductive path through the first p-type well to a third terminal; a gate structure of a transistor over and partially overlapping the first n-type well and the first p-type well; a first n+ type doped region in the first n-type well; a drain terminal of the transistor over and in contact with the first n+ type doped region; a source terminal of the transistor over the first p-type well, wherein the deep n-type well comprises a thickness thicker than a thickness of the deep p-type well, the thickness of the deep p-type well is selected based on a voltage applied to the deep p-type well from the third terminal through the third conductive path, a ratio of the thickness of the deep p-type well to the thickness of the deep n-type well is 2:3, and the thickness of the deep n-type well is selected based on a voltage punch-through. |
地址 |
TW |