Graphics processing architecture employing a unified shader

摘要

A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

主权项

1. A graphics processor, comprising:
a unified shader; and an arbiter circuit operative to carry out an arbitration scheme to determine which of a plurality of inputs to provide to the unified shader; wherein the unified shader is operatively coupled to the arbiter circuit and comprises:
a processor unit configured to simultaneously perform vertex manipulation operations and pixel manipulation operations based on the provided inputs to the unified shader.