发明名称 Memory array with redundant bits and memory element voting circuits
摘要 An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.
申请公布号 US9582374(B2) 申请公布日期 2017.02.28
申请号 US201414269863 申请日期 2014.05.05
申请人 Altera Corporation 发明人 Xu Yanzhong
分类号 G06F11/18;G11C5/00;G11C11/412 主分类号 G06F11/18
代理机构 Treyz Law Group, P.C. 代理人 Treyz Law Group, P.C. ;Milhollin Andrew C.
主权项 1. A method, comprising: with a plurality of thyristor-based memory cells in a memory element, storing redundant data; and with a voting circuit in the memory element, receiving signals from the thyristor-based memory cells and producing a corresponding output for the memory element, wherein the corresponding output is correct even when the thyristor-based memory cells contain only one correct bit and two erroneously flipped bits.
地址 San Jose CA US