主权项 |
1. An interface circuit that receives a differential input signal having a first voltage amplitude from a first circuit, and that outputs an output signal having a second voltage amplitude to a second circuit, the interface circuit comprising:
a level shifter that comprises a first CMOS inverter and a second CMOS inverter which are cross-coupled, and a current limiting circuit that limits a current that flows through the first CMOS inverter and the second CMOS inverter, and that converts the input signal into an intermediate signal which is a differential signal; and a latch circuit that receives the intermediate signal from the level shifter, and that switches a state thereof according to a positive signal and an negative signal of the intermediate signal, wherein the first CMOS inverter comprises: a first NMOS transistor having its gate coupled to an output of the second CMOS inverter; a second NMOS transistor having its source coupled to a drain of the first NMOS transistor, having its drain coupled to an output of the first CMOS inverter, and having its gate receiving a positive signal of the input signal; a first PMOS transistor having its gate receiving the positive signal of the input signal; and a fifth PMOS transistor having its source coupled to a drain of the first PMOS transistor, having its drain coupled to the output of the first CMOS inverter, and having its gate receiving a ground voltage, and wherein the second CMOS inverter comprises: a second NMOS transistor having its gate coupled to the output of the first CMOS inverter; a fourth NMOS transistor having its source coupled to a drain of the second NMOS transistor, having its drain coupled to the output of the second CMOS inverter, and having its gate receiving a negative signal of the input signal; a second PMOS transistor having its gate receiving the negative signal of the input signal; and a sixth PMOS transistor having its source coupled to a drain of the second PMOS transistor, having its drain coupled to the output of the second CMOS inverter, and having its gate receiving a ground voltage. |