发明名称 Using waveform propagation for accurate delay calculation
摘要 Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.
申请公布号 US9582626(B1) 申请公布日期 2017.02.28
申请号 US201414549424 申请日期 2014.11.20
申请人 Cadence Design Systems, Inc. 发明人 Keller Igor;Pramono Eddy;Chen Jijun;Rubanov Nikolay
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Andrews Kurth Kenyon LLP 代理人 Andrews Kurth Kenyon LLP
主权项 1. A method for a static timing analysis of an integrated circuit design, the method comprising: on a computer device having a processor configured to simulate, with a simulator, timing of the circuit design: for each stage from a plurality of stages of the circuit design: retrieving, from a memory, a single waveform having timing and voltage information,modeling execution of the stage using the retrieved single waveform as an input into the stage,when the modeling execution of the stage results in two or more waveforms at a same timing pin, generating a merged waveform based on the two or more waveforms, andstoring an output waveform of the modeled stage in the memory for later use; andsimulating, with the simulator, the static timing analysis for the circuit design based on the modeled stages.
地址 San Jose CA US