发明名称 |
Reduction of defect induced leakage in III-V semiconductor devices |
摘要 |
A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm−2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer. |
申请公布号 |
US9583562(B2) |
申请公布日期 |
2017.02.28 |
申请号 |
US201514745146 |
申请日期 |
2015.06.19 |
申请人 |
International Business Machines Corporation |
发明人 |
de Souza Joel P.;Kim Jeehwan;Sadana Devendra K.;Wacaser Brent A. |
分类号 |
H01L33/00;H01L29/06;H01L29/24;H01L29/201;H01L29/78;H01L29/66;H01L29/08;H01L29/10;H01L29/207 |
主分类号 |
H01L33/00 |
代理机构 |
Tutunjian & Bitetto, P.C. |
代理人 |
Tutunjian & Bitetto, P.C. ;Percello Louis J. |
主权项 |
1. A method for forming a semiconductor device, comprising:
providing a p-doped layer including a doped III-V material on a Si substrate wherein lattice mismatch between the III-V material and the Si substrate provides a dislocation density exceeding 108 cm−2; and reducing leakage current in the device by forming an n-type layer including ZnO on or in the p-doped layer such that the n-type layer can tolerate the dislocation density to form an electronic device where the leakage current is less than that of a device with a III-V n-type layer. |
地址 |
Armonk NY US |