发明名称 |
Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same |
摘要 |
A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm. |
申请公布号 |
US9583485(B2) |
申请公布日期 |
2017.02.28 |
申请号 |
US201514737066 |
申请日期 |
2015.06.11 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Chang Chai-Wei;Chang Che-Cheng;Wu Po-Chi;Chao Yi-Cheng |
分类号 |
H01L27/088;H01L29/06;H01L29/423;H01L29/66;H01L21/3213;H01L21/8234 |
主分类号 |
H01L27/088 |
代理机构 |
Slater Matsil, LLP |
代理人 |
Slater Matsil, LLP |
主权项 |
1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
forming a fin structure over a substrate, wherein the substrate comprises a first region and a second region; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an inter-layer dielectric (ILD) structure over the substrate and adjacent to the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first trench and a second trench in the ILD structure; forming a first gate structure in the first trench and a second gate structure in the second trench, wherein the first gate structure comprises a first work function layer, and the second gate structure comprises a second work function layer; performing a first plasma operation on the first work function layer and the s_econd work function layer for a first period of time; and performing a second plasma operation at zero bias power on the first work function layer and the second work function layer for a second period of time such that after performing the first plasma operation and the second plasma operation, the first work function layer has a first height, and the second work function layer has a second height, and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm. |
地址 |
Hsin-Chu TW |