Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping

摘要

A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module in first clock cycle. Next, it comprises determining if a first physical register file unit has capacity to support instructions dispatched in the first clock cycle. Further, it comprises supplying a response back to logic circuitry between the plurality of select ports and a plurality of execution ports, wherein the logic circuitry is operable to re-map select ports in the scheduler module to execution ports based on the response. Finally, responsive to a determination that the first physical register file unit is full, the method comprises re-mapping at least one select port connecting with an execution unit in the first physical register file unit to a second physical register file unit.

主权项

1. A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor, said method comprising:
selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module of the microprocessor in a first clock cycle; determining if a first physical register file unit has capacity to support instructions dispatched in said first clock cycle; supplying a response to said determining to logic circuitry coupled between said plurality of select ports and a plurality of execution ports of a plurality of execution units of the microprocessor, wherein said logic circuitry is operable to re-map select ports in said scheduler module to execution ports based on said response; and responsive to a determination that said first physical register file unit is full, re-mapping at least one select port connected with a first execution port of a first execution unit associated with said first physical register file unit to a second execution port of a second execution unit associated with a second physical register file unit, wherein said second physical register file unit has capacity to support an instruction dispatched from said at least one select port.