Integrated circuit structure and method for reducing polymer layer delamination

摘要

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

主权项

1. An integrated circuit structure comprising:
a substrate; a metal pad over the substrate; a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad; a first polymer layer over the PPI structure, the first polymer layer including an untreated portion and a treated portion, the treated portion having a higher hydrogen concentration than the untreated portion; an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, wherein a sidewall of the UBM is aligned with a sidewall of the treated portion of the first polymer layer and wherein the UBM extends over the untreated portion and does not extend over the treated portion layer; and the treated portion of the first polymer layer forming a barrier layer on a top surface of the untreated portion of the first polymer layer adjacent to the UBM, the barrier layer being nonconductive, wherein the barrier layer does not extend into the first portion of the top surface of the first polymer layer, a top surface of the treated portion of the first polymer layer being co-planar with a bottom surface of the UBM.