BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN DIGITAL TO ANALOG CONVERTERS

摘要

System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.

主权项

1. A method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), comprising:
a) introducing a set of two samplers with adjustable sample time and threshold, at the output of said DAC, which are separated in time; b) sweeping said set of samplers through a n unit interval (UI) window; c) classifying said n-UI window to periods of transitions and non-transitions on an eye diagram; d) controlling the relative timing of the lower rate clocks into an n:1 multiplexer using a control loop, to force equal eye width within said n-UI window; and e) measuring and correcting the interleaved timing errors, until the uneven distribution is being reduced below a predetermined level.