DISLOCATION STRESS MEMORIZATION TECHNIQUE (DSMT) ON EPITAXIAL CHANNEL DEVICES

摘要

The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

主权项

1. A transistor device, comprising:
an epitaxial source region arranged within a substrate; an epitaxial drain region arranged within the substrate and separated from the epitaxial source region by a channel region; and first and second dislocation stress memorization (DSM) regions comprising stressed lattices configured to generate stress within the channel region, wherein the first DSM region extends from below the epitaxial source region to a first location within the epitaxial source region and the second DSM region extends from below the epitaxial drain region to a second location within the epitaxial drain region.