| 发明名称 |
MEMORY SYSTEM AND CACHE MEMORY |
| 摘要 |
A memory system has a non-volatile memory including a plurality of circuit blocks using different voltages, a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off, and a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry. |
| 申请公布号 |
US2017053689(A1) |
申请公布日期 |
2017.02.23 |
| 申请号 |
US201615267206 |
申请日期 |
2016.09.16 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
NOGUCHI Hiroki;FUJITA Shinobu |
| 分类号 |
G11C11/16;G06F12/0893;G06F1/32 |
主分类号 |
G11C11/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory system, comprising:
a non-volatile memory including a plurality of circuit blocks using different voltages; a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry. |
| 地址 |
Tokyo JP |
