MITIGATING WIRE CAPACITANCE IN AN INTEGRATED CIRCUIT

摘要

Systems, methods, and other embodiments associated with mitigating wire capacitance are described. In one embodiment, a method includes loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit. The design defines layers of the integrated circuit and connections between structures and wire interconnects in the layers. The example method may also include generating, by at least the processor, a structured topology in the design by successively routing the wire interconnects throughout the layers according to coordinates of the structures in the design and weighted values associated with each of the structures to mitigate wire capacitance of the wire interconnects.

主权项

1. A non-transitory computer-readable medium storing computer-executable instructions that when executed by a computer cause the computer to perform functions, the computer-executable instructions comprising instructions for:
loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit; locating, by at least the processor, structures that are to be electrically connected together by determining coordinates of the structures within the design; and generating, by at least the processor, a structured topology in the design to electrically connect the structures by successively routing wire interconnects in layers of the design according to the coordinates of the structures and a weighted value associated with each of the structures.