METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

摘要

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

主权项

1. A first integrated circuit to communicate with a second integrated circuit over at least one conductive path, the first integrated circuit comprising:
a transmitter to transmit information from the first integrated circuit to the second integrated circuit over a first conductive path, the transmitter including a transmit equalizer; a receiver to receive information from the second integrated circuit over one of the first conductive path, or a second conductive path; and a circuit to generate equalization settings for the transmit equalizer responsive to inter-symbol interference affecting the transmission of the information transmitted to the first integrated circuit from the second integrated circuit.