发明名称 N-BIT COMPARE LOGIC WITH SINGLE-ENDED INPUTS
摘要 Disclosed systems and methods relate to comparison of a first number and a second number. A comparator receives first and second single-ended inputs (i.e., not represented in differential format), which may be n-bits wide, wherein the first input is an inverted version of the first number and the second input is a true version of the second number. A partial match circuit is implemented to generate a partial match output based only on the first single-ended input and the second single-ended input. A partial mismatch circuit is implemented to generate a partial mismatch output based only on the first single-ended input and the second single-ended input. A comparison output circuit is implemented to generate a comparison output of the first and second numbers based on the partial match output and the partial mismatch output.
申请公布号 WO2017030680(A1) 申请公布日期 2017.02.23
申请号 WO2016US41903 申请日期 2016.07.12
申请人 QUALCOMM INCORPORATED 发明人 GARG, Manish;ADAIKKALAVAN, Ramasamy
分类号 G06F7/02 主分类号 G06F7/02
代理机构 代理人
主权项
地址