| 主权项 |
1. A display apparatus comprising:
a printed circuit board (PCB); a power management integrated circuit (PMIC) mounted on the PCB, wherein the PMIC is configured to generate first, second, third and fourth gate clock signals and first, second, third and fourth inversion gate clock signals, wherein a phase of the first gate clock signal partially overlaps a phase of the second, third or fourth gate clock signal, wherein each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals; a gate driver configured to generate a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals, wherein the gate driver is configured to apply the plurality of gate signals to a plurality of gate lines; and a display panel connected to the plurality of gate lines, wherein the PCB includes:
an insulation layer;first, second, third and fourth lines disposed on a first surface of the insulation layer, wherein the first to fourth lines transmit the first to fourth gate clock signals, respectively; andfifth, sixth, seventh and eighth lines disposed on a second surface of the insulation layer, wherein the second surface of the insulation layer faces the first surface of the insulation layer, wherein the fifth to eighth lines transmit the first to fourth inversion gate clock signals, respectively. |
