发明名称 |
SILICON CARBIDE SEMICONDUCTOR DEVICE |
摘要 |
The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer, a well region, a source region, a channel resistance adjusting region, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The channel resistance adjusting region is sandwiched between the source region and the SiC epitaxial layer in a surface layer of the well region. The channel resistance adjusting region is a region in which a first impurity region is intermittently formed in a direction intersecting a direction in which the source region and the SiC epitaxial layer sandwich the channel resistance adjusting region. |
申请公布号 |
US2017054017(A1) |
申请公布日期 |
2017.02.23 |
申请号 |
US201415307835 |
申请日期 |
2014.06.27 |
申请人 |
Mitsubishi Electric Corporation |
发明人 |
TAKAKI Yasushi;TARUI Yoichiro |
分类号 |
H01L29/78;H01L29/10;H01L21/265;H01L29/06;H01L29/167;H01L29/08;H01L29/16 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
1. A silicon carbide semiconductor device, comprising:
an epitaxial layer of a first conductive type formed on an upper surface of a silicon carbide semiconductor substrate; a well region of a second conductive type formed partially in a surface layer of said epitaxial layer; a source region of the first conductive type formed partially in a surface layer of said well region; a channel resistance adjusting region sandwiched between said source region and said epitaxial layer in the surface layer of said well region; a gate electrode formed on an upper surface of said channel resistance adjusting region with a gate insulating film interposed therebetween; an interlayer insulating film formed to cover said gate electrode; a source electrode formed on an upper surface of said interlayer insulating film and an upper surface of said source region; and a drain electrode formed on a lower surface of said silicon carbide semiconductor substrate, wherein said channel resistance adjusting region is a region in which a first impurity region of the first conductive type or a second impurity region of the second conductive type is intermittently formed in a direction intersecting a direction in which said source region and said epitaxial layer sandwich said channel resistance adjusting region; an impurity concentration of said first impurity region is higher than an impurity concentration of said epitaxial layer when said channel resistance adjusting region is a region in which said first impurity region is intermittently formed; and an impurity concentration of said second impurity region is higher than an impurity concentration of said well region when said channel resistance adjusting region is a region in which said second impurity region is intermittently formed. |
地址 |
Tokyo JP |