ANTIFUSE-TYPE ONE TIME PROGRAMMING MEMORY CELL AND ARRAY STRUCTURE WITH SAME

摘要

An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.

主权项

1. An antifuse-type OTP memory cell, comprising:
a well region; a first doped region, a second doped region, a third doped region and a fourth doped region formed in a surface of the well region; a gate oxide layer covering the surface of the well region; a first gate formed on the gate oxide layer and spanned over the first doped region and the second doped region, wherein the first gate is connected with a word line; a second gate formed on the gate oxide layer and spanned over the second doped region and the third doped region, wherein the second gate is connected with an antifuse control line; a third gate formed on the gate oxide layer and spanned over the third doped region and the fourth doped region, wherein the third gate is connected with an isolation control line; and a first metal layer connected with the first doped region through a via, wherein the first metal layer is a bit line.