发明名称 CLOCK RECOVERY METHOD & APPARATUS
摘要 A method and apparatus for clock recovery is provided. The method begins when a reference pulse is extracted from a signal. This reference pulse is then compared with a clock signal. A phase of the extracted reference signal is then detected, and is done in relation to the clock signal. Phase differences between the extracted reference signal with respect to the clock signal are accumulated over a predetermined period of time. This accumulating continues until a predetermined number of phase differences has been accumulated. The accumulated phase differences are then averaged. The apparatus includes: a phase detector; a phase averaging unit in communication with a clock generator and a controller; a lock detector in communication with the phase averaging unit and a loop filter; at least one adder; at least one bypass filter; and at least one accumulator.
申请公布号 US2017054548(A1) 申请公布日期 2017.02.23
申请号 US201514831826 申请日期 2015.08.20
申请人 Macnica Americas, Inc. 发明人 Culley David Heath
分类号 H04L7/033;H04L7/00 主分类号 H04L7/033
代理机构 代理人
主权项 1. A method of clock recovery, comprising: extracting a reference pulse from an incoming data stream without a reference clock; comparing the extracted reference pulse with a generated clock signal; detecting a phase difference of the extracted reference pulse in relation to the generated clock signal; accumulating a phase difference of the extracted reference pulse with respect to the generated clock signal over a predetermined number of samples until a number of phase differences is reached; determining if the magnitude of the accumulated phase difference is increasing or decreasing, or if the sign of the accumulated phase difference has changed; computing a frequency error from the accumulated phase difference, wherein if the phase difference magnitude is increasing, or if the sign has changed, inversely adjusting the frequency error; comparing the frequency error with an upper limit and a lower limit; determining if the frequency error is trending to exceed a bounds defined by the upper and lower limit adjusting a generated clock output frequency using the frequency error to produce a new clock frequency; and using the new clock frequency as the generated clock signal to produce a clock-synchronized signal.
地址 Solana Beach CA US