| 摘要 |
PROBLEM TO BE SOLVED: To provide a test circuit capable of shortening test time and specifying a circuit generating a failure.SOLUTION: A memory chip test circuit includes: a determination circuit for outputting a first determination signal expressing whether an internal circuit is normally operated or not and a second determination signal expressing whether read data coincide with expected value data or not; a test result signal generation circuit for switching a change detection signal of the second determination signal and a memory clock in accordance with a change detection signal of the first determination signal and outputting a first test result signal; a failure separation circuit which outputs a switching signal expressing whether both of a first case where write data before and after passing a mode switching circuit coincide with each other and a second case where the memory clock is normally operated exist or not, and when at least one of the first case and the second case does not exist, outputs error data which is a fixed value; and a test result output circuit for switching the first test result signal and the error data in accordance with the switching signal and outputting a second test result signal. |
