发明名称 MES構造トランジスタを作製する方法、MES構造トランジスタ
摘要 PROBLEM TO BE SOLVED: To provide a method for fabricating an MES structure transistor capable of reducing effects of a current collapse phenomenon.SOLUTION: A first silicon nitride film 27 is formed so as to abut on a gallium nitride-based semiconductor layer 13 by starting growth under a condition in which a first membrane stress can be supplied. Because the absolute value of the first membrane stress of this first silicon nitride film 27 is smaller than the absolute value of a second membrane stress of a second silicon nitride film 29, an interface-state density at a boundary surface between the silicon nitride and the gallium nitride-based semiconductor can be reduced. A silicon nitride film 29 is formed on the silicon nitride film 27 by performing growth under a condition in which the second membrane stress can be supplied. Because the absolute value of the second membrane stress of this silicon nitride film 29 is larger than the absolute value of the first membrane stress of the silicon nitride film 27, a trapping-level density of the silicon nitride film 29 can be reduced, and because a trapping-level density in an SiN film decreases, a current collapse can be reduced.
申请公布号 JP6085178(B2) 申请公布日期 2017.02.22
申请号 JP20130007495 申请日期 2013.01.18
申请人 住友電気工業株式会社;国立大学法人東北大学 发明人 渡邊 整;辻 幸洋;寺本 章伸
分类号 H01L21/338;H01L21/318;H01L29/778;H01L29/812 主分类号 H01L21/338
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