| 摘要 |
PROBLEM TO BE SOLVED: To achieve a Hall element structure with small offset voltage without using a nonvolatile memory, and provide a Si monolithic Hall element with a small systematic offset voltage and a method of manufacturing the same.SOLUTION: A Hall element 10 includes: a p-type semiconductor substrate layer 11 composed of a p-type silicon; an n-type impurity region 12 provided on a surface of the p-type semiconductor substrate layer 11; a first p-type region 13a provided in a surface of the n-type impurity region 12; n-type regions 14a provided in a surface of the n-type impurity region 12 and on both sides of the first p-type region 13a; a p-type impurity region 15a provided on both sides of the n-type impurity region 12; a second p-type region 13b provided in a surface of the p-type impurity region 15a; and a dummy-pattern n-type impurity region 19 provided on boths of the p-type impurity region 15a. |
