Multi-device memory serial architecture

摘要

Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.

主权项

1. A method of operating a memory device, the method comprising:
determining a particular memory device of a plurality of memory devices, connected via a chain topology comprising serial bidirectional interconnections between memory devices, to electronically access based on a command from a processor; transmitting at least one signal from a memory controller directly via a conducting line to a switch within the particular memory device, wherein the conducting line is separate from the bidirectional interconnections; electrically connecting a memory array of the particular memory device to a bidirectional interconnection interface of the particular memory device in response to the at least one signal while electrically disconnecting a memory array of a memory device between the memory controller and the particular memory device; and while the memory of the memory device between the memory controller and the particular memory device is electrically disconnected, electrically connecting the memory array of the particular memory device indirectly to the memory controller via the bidirectional interconnections through the memory device between the memory controller and the particular memory device.