| 摘要 |
A decision feedback equalizer (DFE) includes first through sixth flip-flops, and first and second summer circuits. The first through fourth flip-flops sample an analog input signal received at the first and second summer circuits, detect the logic level of a data bit in the analog input signal and generate the first through fourth compensated signals. The first multiplexer outputs at least one of the first and second compensated signals as a first feedback signal, based on a fourth feedback signal generated by the sixth flip-flop. The second multiplexer outputs at least one of the third and fourth compensated signals as a second feedback signal, based on a third feedback signal generated by the fifth flip-flop. The first and second feedback signals are multiplied by a weight coefficient and fed back to the first and second summer circuit, respectively, to compensate an error in the analog input signal. |
| 主权项 |
1. A decision feedback equalizer (DFE), comprising:
first and second summer circuits for receiving an analog input signal, and first and second weighted feedback signals and generating first and second intermediate signals, respectively, wherein the first and second weighted feedback signals have a first predetermined phase difference therebetween; a first flip-flop having a first input terminal connected to the first summer circuit for receiving the first intermediate signal, a clock input terminal for receiving a first clock signal, a second input terminal for receiving a first offset voltage value, and an output terminal for generating a first compensated signal; a second flip-flop having a first input terminal connected to the first summer circuit for receiving the first intermediate signal, a clock input terminal for receiving the first clock signal, a second input terminal for receiving an inverted first offset voltage value, and an output terminal for generating a second compensated signal; a third flip-flop having a first input terminal connected to the second summer circuit for receiving the second intermediate signal, a clock input terminal for receiving a second clock signal, a second input terminal for receiving the first offset voltage value, and an output terminal for generating a third compensated signal; a fourth flip-flop having a first input terminal connected to the second summer circuit for receiving the second intermediate signal, a clock input terminal for receiving the second clock signal, a second input terminal for receiving the inverted first offset voltage value, and an output terminal for generating a fourth compensated signal, wherein the first and second clock signals have the first predetermined phase difference therebetween; a first multiplexer having first and second input terminals for receiving the first and second compensated signals, respectively, a select terminal for receiving a first select signal, and an output terminal for outputting at least one of the first and second compensated signals as a first feedback signal; a first feedback generator connected to the output terminal of the first multiplexer for receiving the first feedback signal and generating the first weighted feedback signal, wherein the first feedback generator is connected to the first summer circuit for providing the first weighted feedback signal thereto; a second multiplexer having first and second input terminals for receiving the third and fourth compensated signals, a select terminal for receiving a second select signal, and an output terminal for outputting at least one of the third and fourth compensated signals as a second feedback signal; a second feedback generator connected to the output terminal of the second multiplexer for receiving the second feedback signal and generating the second weighted feedback signal, wherein the second feedback generator is connected to the second summer circuit for providing the second weighted feedback signal thereto; a fifth flip-flop having a first input terminal connected to the output terminal of the first multiplexer for receiving the first feedback signal, a clock input terminal for receiving a third clock signal, and an output terminal for outputting a third feedback signal, wherein the select terminal of the second multiplexer is connected to the output terminal of the fifth flip-flop for receiving the third feedback signal as the second select signal; and a sixth flip-flop having a first input terminal connected to the output terminal of the second multiplexer for receiving the second feedback signal, a clock input terminal for receiving a fourth clock signal, and an output terminal for outputting a fourth feedback signal, wherein the select terminal of the first multiplexer is connected to the output terminal of the sixth flip-flop for receiving the fourth feedback signal as the first select signal, wherein the third and fourth clock signals have the first predetermined phase difference therebetween, wherein the first and third clock signals, and the second and fourth clock signals have a second predetermined phase difference therebetween, wherein the second and third clock signals, and the first and fourth clock signals have a third predetermined phase difference therebetween, and whereby the first and second weighted feedback signals compensate an error in the analog input signal. |
