Error correction in a memory device

摘要

A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

主权项

1. A memory controller comprising:
an interface configured to be communicatively coupled to a memory array; and control circuitry configured to select a subset of the memory array for protection using error-correcting code (ECC), the control circuitry 1) selecting a portion of at least one memory segment having a plurality of cells configured to store ECC information associated with the memory array, and 2) linking the subset of the memory array selected to a portion of the at least one memory segment such that the subset is protected by the ECC.