Mixed-width memory techniques for programmable logic devices

摘要

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

主权项

1. A computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD); and synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:
detecting a mixed-mode memory operation in the design, the mixed-mode memory operation specifying memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width, each of the plurality of embedded memory blocks being associated with a corresponding write enable signal to be used for enabling each embedded memory block for writing,determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, andmodifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks, the modifying comprising generating a write mask signal for each of the reduced number of embedded memory block, using the write enable signals, to allow a plurality of data portions to be written without overwriting each other in the reduced number of embedded memory blocks.