FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

摘要

A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

主权项

1. A semiconductor device comprising:
a gate structure present on at least one suspended channel structure, wherein at least one gate dielectric layer is present surrounding, and in contact with, the at least one suspended channel structure and at least one gate conductor is present on the at least one gate dielectric layer; and source and drain structures comprised of a strain inducing material, wherein the source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a semiconductor cladding layer formed on sidewalls of the source and drain ends of the suspended channel structure, wherein a lattice dimension of the strain inducing material is different from a lattice dimension of the semiconductor cladding layer.