Fractional phase locked loop (PLL) architecture

摘要

In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

主权项

1. A frequency divider, comprising:
a plurality of cascaded divider stages forming a divider chain, wherein each of the divider stages is configured to receive one or more respective control bits and to set a divider value of the divider stage based on the one or more respective control bits, and wherein the plurality of cascaded divider stages is configured to propagate an input signal down the divider chain from a first one of the divider stages to a last one of the divider stages, to divide a frequency of the input signal, and to propagate a modulus signal up the divider chain from the last one of the divider stages to the first one of the divider stages, and each of the divider stages is configured to output a respective local load signal when the modulus signal propagates out of the divider stage; and an extension device coupled to the plurality of divider stages, wherein, for each of the divider stages, the extension device is configured to receive the respective local load signal from the divider stage and to input the one or more respective control bits for the divider stage to the divider stage based on the respective local load signal.