发明名称 |
Transistor structure with reduced parasitic side wall characteristics |
摘要 |
A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation). |
申请公布号 |
US9577039(B2) |
申请公布日期 |
2017.02.21 |
申请号 |
US201414585211 |
申请日期 |
2014.12.30 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
Rothleitner Hubert |
分类号 |
H01L29/06;H01L29/423;H01L29/78;H01L29/49;H01L29/66;H01L29/10 |
主分类号 |
H01L29/06 |
代理机构 |
Viering, Jentschura & Partner MBB |
代理人 |
Viering, Jentschura & Partner MBB |
主权项 |
1. A transistor structure, comprising:
a substrate; a well region of a first impurity type in the substrate; at least one transistor formed at least partially on the well region, a portion of the well region comprising a transistor channel; a structure of the first impurity type in the substrate enclosing the well region; and an isolation layer on a portion of the substrate surrounding the structure; wherein a concentration of the first impurity type in the structure enclosing the well region is higher than a concentration of the first impurity type in the well region. |
地址 |
Neubiberg DE |