发明名称 Complementary metal oxide semiconductor transistor and fabricating method thereof
摘要 A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
申请公布号 US9577011(B2) 申请公布日期 2017.02.21
申请号 US201514720997 申请日期 2015.05.26
申请人 Au Optronics Corporation 发明人 Chen Chung-Tao;Chiu Ta-Wei;Lin Yu-Pu;Chen Yi-Wei
分类号 H01L27/28;H01L27/12;H01L29/786;H01L29/66;H01L21/441;H01L21/467;H01L51/05;H01L51/00 主分类号 H01L27/28
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A fabricating method of a complementary metal oxide semiconductor transistor comprising: forming a first channel layer on a substrate; forming a bottom gate, a first source, and a first drain on the substrate, wherein the first source and the first drain are in contact with the first channel layer, and the first channel layer is formed before the first source and the first drain are formed; forming a gate insulator on the substrate to cover the bottom gate, the first source, and the first drain; forming a second channel layer on the gate insulator, wherein the second channel layer is located above the bottom gate; forming a top gate, a second source, and a second drain on the gate insulator, wherein the top gate is located above the first channel layer, and the second source and the second drain are in contact with the second channel layer; forming a passivation layer, the passivation layer covering the second channel layer, the gate insulator, the second source, the second drain, and the top gate; patterning the passivation layer to form a plurality of first contact holes in the passivation layer and the gate insulator and form a plurality of second contact holes in the passivation layer, wherein the first contact holes expose the first source and the first drain, and the second contact holes expose the second source and the second drain; and forming a plurality of first contact conductors and a plurality of second contact conductors on the passivation layer, wherein the first contact conductors are electrically connected to the first source and the first drain through the first contact holes, and the second contact conductors are electrically connected to the second source and the second drain through the second contact holes.
地址 Hsinchu TW