Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters

摘要

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

主权项

1. An analog-to-digital converter (ADC) for converting an analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide a digital output signal, comprising:
a successive approximation register (SAR) segment, including a first array of switchable capacitors from among a plurality of switchable capacitors, the plurality of switchable capacitors being configured to capture one or more samples of the analog input signal during a sampling phase, each switchable capacitor from among the first array of switchable capacitors being configured to switch between a first reference voltage and a second reference voltage based upon a polarity of the one or more samples of the analog input signal during a conversion phase; an excess loop delay compensation (ELDC) segment including a second array of switchable capacitors from among the plurality of switchable capacitors, each switchable capacitor from among the second array of switchable capacitors being configured to switch between the first reference voltage and the second reference voltage based upon a previous value of the digital output signal to provide a discrete representation of the analog input signal during the conversion phase; and a comparator configured to convert the discrete representation of the analog input signal to the digital signal domain to provide the digital output signal.