Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation

摘要

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

主权项

1. A system for wireless communication, the system comprising:
a chip comprising one or more circuits, said one or more circuits comprising a time interleaved analog-to-digital-converter (ADC) and timing offset estimation and compensation circuitry, wherein said one or more circuits are operable to:
receive an analog signal on said chip;convert the analog signal to a digital signal utilizing said time interleaved ADC; andreduce a blocker signal that is aliased onto a desired signal by timing offsets in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital output signal and said blocker signal.