Current balance method and current balance circuit thereof

摘要

The present disclosure illustrates a current balance method and a current balance circuit thereof. The current balance method is used in a multiphase digital pulse width modulator. Steps of the current balance method are as follows. A plurality of pulse width values of the pulse width modulated signals within a first period are recorded, and a minimum pulse width value is defined as a standard value. The method determines whether each pulse width value is larger than the sum of the standard value and a pulse width threshold, and if yes, the method adds 1 to a count value of the phase output stage corresponding to the pulse width value. The method determines whether each count value equals to a counting threshold, and if yes, the method adjusts the pulse width modulated signal, and initializing the count value as 0.

主权项

1. A current balance method for avoiding an output current of a multiphase digital pulse width modulator to diverge, wherein the multiphase digital pulse width modulator periodically outputs M pulse width modulated signals to M phase output stages of the multiphase digital pulse width modulator respectively and M is a positive integer greater than or equal to 2, and the current balance method comprising:
(A) recording, by a recording and comparing circuit, a pulse width value of the pulse width modulated signal output into each phase output stage within a first period of the multiphase digital pulse width modulator, and obtaining a minimum pulse width value among the pulse width values as a standard value; (B) respectively determining, by a first operation processing circuit, whether the pulse width value of each phase output stage is larger than a sum of the standard value and a pulse width threshold, and adding 1 to a count value of the phase output stage corresponding to the pulse width value, if the pulse width value of each phase output stage is larger than the sum of the standard value and the pulse width threshold; and (C) respectively determining, by a second operation processing circuit, whether the count value of each phase output stage equals to a counting threshold, adjusting the pulse width modulated signal, output to the phase output stage corresponding to the count value within a second period by the multiphase digital pulse width modulator, if the count value of each phase output stage equals to the counting threshold, and initializing the count value as 0; wherein in the step (B), determining not to add 1 to the count value of the phase output stage corresponding to the pulse width value, if the pulse width value of each phase output stage is not larger than the sum of the standard value and the pulse width threshold; wherein in the step (C), determining not to adjust the pulse width modulated signal output to the phase output stage corresponding to the count value within a second period by the multiphase digital pulse width modulator, if the count value of each phase output stage is not equal to the counting threshold.