Memory device with reduced test time

摘要

In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.

主权项

1. A method comprising:
causing, by a test system releasably coupled to a memory device, the memory device to perform, on a memory space corresponding to an address:
a series of read operations and write operations;a first operation to read a first set of data bits and a first set of parity bits from the memory space corresponding to the address;a second operation to generate a second set of parity bits from the first set of data bits;a third operation to generate a multi-dimensional array representative of a location and a number of errors in the first set of data bits and the first set of parity bits;a fourth operation to generate a second set of data bits based at least in part on the first set of data bits and the multi-dimensional array; receiving, at the test system from the memory device, the multi-dimensional array and the second set of data bits; performing, by the test system, a first comparison of the multi-dimensional array to an expected result to identify the location and the number of errors within the first set of data bits and the first set of parity bits, the location and the number of errors within the first set of data bits and the first set of parity bits representative of errors that occurred with an error correction unit of the memory device disabled; performing, by the test system, a second comparison including comparing the second set of data bits to expected data to identify a location and a number of errors within the second set of data bits, the location and the number of errors within the second set of data bits representative of errors that occurred with the error correction unit of the memory device enabled; and binning, by the test system, the memory device as usable or unusable based at least in part on the number of errors within the first set of data bits and the first set of parity bits and the number of errors within the second set of data bits.