Translation entry invalidation in a multithreaded data processing system

摘要

In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

主权项

1. A processing unit for a multithreaded data processing system including a plurality of processor cores, the processing unit comprising:
a processor core including:
a translation structure that caches address translations;a memory management unit that translates effective addresses to real addresses by reference to the translation structure;an execution unit that concurrently executes a plurality of hardware threads, wherein an initiating thread among the plurality of hardware threads generates a translation invalidation request by execution of a corresponding translation invalidation instruction; a shared queue that receives storage-modifying requests of the plurality of concurrently executing hardware threads, wherein the plurality of storage-modifying requests includes the translation invalidation request; sidecar logic coupled to the shared queue, wherein the sidecar logic includes a plurality of sidecars each associated with a respective one of the plurality of hardware threads, and wherein the processing unit is configured to perform:
pausing dispatch of instructions within the initiating thread that follow the translation invalidation instruction in program order and resuming dispatch of instructions within the initiating thread in response to receipt of an acknowledgment signal confirming completion of processing of the translation invalidation request at the processor core;in response to receiving the translation invalidation request in the shared queue, removing the translation invalidation request from the shared queue and buffering the translation invalidation request in a sidecar associated with the initiating thread;while the translation invalidation request is buffered in the sidecar, broadcasting the translation invalidation request such that the translation invalidation request is received and processed by the plurality of processor cores;in response to confirmation of completion of processing of the translation invalidation request by the processor core, removing the translation invalidation request from the sidecar; andensuring completion of processing of the translation invalidation request at all of the plurality of processor cores by a broadcast synchronization request.