发明名称 |
Detecting single event upsets and stuck-at faults in RAM-based data path controllers |
摘要 |
In one embodiment, a system includes a processor and logic configured to receive data including a plurality of data elements, each data element having one or more bits, and pass each data element along with a corresponding parity bit to an input of a data path, a first binary sequence generator configured to create a binary sequence having a plurality of bonus bits, wherein a total length of the binary sequence is equal to or greater than a maximum burst size of the data, and a first parity module configured to provide a parity calculation using bits of each data element of the data with a bonus bit from the binary sequence to produce a parity bit for each data element. Other systems, methods, and computer program products for providing end-to-end parity generation and checking that the scheme provides coverage for both data and sequencing faults are also disclosed. |
申请公布号 |
US9575834(B2) |
申请公布日期 |
2017.02.21 |
申请号 |
US201414280424 |
申请日期 |
2014.05.16 |
申请人 |
International Business Machines Corporation |
发明人 |
Pierce David A. |
分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
Zilka-Kotab, PC |
代理人 |
Zilka-Kotab, PC |
主权项 |
1. A system, comprising:
a hardware processor and logic integrated with and/or executable by the hardware processor, the logic being configured to:
receive data comprising a plurality of data elements, each data element comprising one or more bits; andpass bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements to an input of a data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length that a predetermined maximum burst size; a first binary sequence generator configured to create a binary sequence comprising a plurality of bonus bits, wherein a total length of the binary sequence is equal to or greater than the predetermined maximum burst size, and wherein the first binary sequence generator comprises a patterned read only memory (ROM) storing values, the ROM being configured for access according to a predetermined pattern to access the values; and a first parity module configured to provide a parity calculation prior to passing the plurality of data elements to the input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element, wherein meta data is included in the parity calculation to produce the parity bit. |
地址 |
Armonk NY US |