Method and system for architecture of a fast programmable transport demultiplexer using a double buffered approach

摘要

A method and system are provided for architecture of a very fast programmable transport demultiplexer using a double-buffered approach. The method may involve utilizing a hardware assist block to process incoming packets, retrieve information about the packets, and write the retrieved information to a memory block. A firmware block may then utilize the information in memory to perform further processing on the packet data. The firmware and hardware assist blocks may work simultaneously so as to speed up the processing of the packet, which can comprise record data and/or audio/video data. The system may comprise the hardware assist block, the firmware assist block, and a memory block.

主权项

1. A system for processing a plurality of packets comprising:
a first circuit configured to:
process at least a portion of a first packet to generate a first partially processed packet by determining at least a first format associated with the first packet;extract information regarding the first packet based on the first format; a memory configured to store the extracted information in a second format different from the first format; and a second circuit configured to process the first partially processed packet based at least in part on the extracted information to generate a first processed packet while the first circuit is processing at least a portion of a second packet to generate a second partially processed packet.