Elastic gear first-in-first-out buffer with frequency monitor

摘要

An elastic gear First-In-First-Out (FIFO) buffer architecture is disclosed. The proposed elastic gear FIFO buffer uses a frequency monitor unit to control clock frequency compensation. By using an independent frequency monitor unit, the data latency and FIFO buffer size are best optimized. An elastic gear FIFO could be utilized in applications where clock compensation and asynchronous data width conversion are desired or required.

主权项

1. An elastic gear First-in-First-out (FIFO) buffer, comprising:
an input that is configured to receive write data from a first device operating with a first local clock domain; a plurality of memory cells that receive and temporarily store the write data received from the input; an output that is configured to provide write data from the plurality of memory cells to a second device operating with a second local clock domain that is different from the first local clock domain; a frequency monitor that controls and monitors a difference between the first local clock domain and the second local clock domain and, based on the difference, determines whether to instruct a pointer movement controller to adjust one or both of a write pointer and a read pointer for the plurality of memory cells, thereby allowing the elastic gear FIFO buffer to balance data flowing from the input to the output; and an elastic reset module that initializes a virtual depth for the plurality of memory cells, wherein the elastic reset module comprises a read reset control and a write reset control, wherein the read reset control include a domain synchronization module and a delay module with a configurable delay.