Predication in a vector processor

摘要

Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.

主权项

1. A system for vector processor predication in an active memory device, the system comprising:
memory in the active memory device; and a processing element in the active memory device, the processing element comprising a vector mask register, an arithmetic logic unit, and a load store unit, the processing element configured to perform a method comprising:
setting one or more mask bits in the vector mask register in the processing element;applying the one or more mask bits by the processing element to predicate operation of the arithmetic logic unit or the load-store unit in the processing element associated with at least one of a plurality of sub-instructions;performing a compare of operands in the processing element using predication of a compare instruction to perform less than a maximum supported number of comparisons in parallel based on the one or more mask bits;storing compare results of the compare instruction as mask bit values of the vector mask register;analyzing a compare instruction syntax bit of the compare instruction to select between performing an OR-reduction and an AND-reduction on the mask bit values stored in response to performing less than the maximum supported number of comparisons in parallel by the predication of the compare instruction;reducing the mask bit values to a summary condition by performing a logical OR combination of the compare results based on determining that the OR-reduction is selected by the compare instruction syntax bit;reducing the mask bit values to the summary condition by performing a logical AND combination of the compare results based on determining that the AND-reduction is selected by the compare instruction syntax bit;writing the summary condition to a condition register; andusing the summary condition of the condition register to determine a branch direction of a conditional branch instruction in the processing element.