Zero cycle move

摘要

A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

主权项

1. A processor comprising:
an architectural register file comprising a plurality of registers; a decoder configured to decode fetched instructions; a register duplication array (RDA) comprising a plurality of entries, wherein said plurality of entries is fewer than said plurality of registers, and wherein each entry is configured to store:
an identification of a given rename register identifier (ID); anda count of mappings to the given rename register ID; and a register rename unit configured to:
maintain the stored counts of mappings for no more than the plurality of entries of the RDA;receive instructions; andin response to determining a given instruction qualifies for a zero cycle move operation:
assign a rename register ID of a source operand of the given instruction to a destination operand of the given instruction;access the RDA with the rename register ID of the source operand of the given instruction;in response to detecting the RDA does not include an entry corresponding to the rename register ID:
allocate a given entry of the RDA for the rename register ID;store an identification of the rename register ID in the given entry; andstore a count of a number of mappings to the rename register ID in the given entry;in response to detecting the RDA includes a previously allocated entry corresponding to the rename register ID, increment a count of a number of mappings to the rename register ID in the previously allocated entry;prevent the given instruction from proceeding in a pipeline of the processor; wherein in response to accessing the RDA for a first instruction of the received instructions, determining the RDA has no allocated entry for the first instruction and the RDA is full, the register rename unit is further configured to access a free list to assign a rename register ID to a destination operand of the first instruction with no storage of a count of a number of mappings to the rename register ID.