发明名称 LOADING DATA USING SUB-THREAD INFORMATION IN A PROCESSOR
摘要 In one embodiment, a processor includes a core to execute instructions, a cache memory coupled to the core, and a cache controller coupled to the cache memory. The cache controller, responsive to a first load request having a first priority level, is to insert data of the first load request into a first entry of the cache memory and set an age indicator of a metadata field of the first entry to a first age level, the first age level greater than a default age level of a cache insertion policy for load requests, and responsive to a second load request having a second priority level to insert data of the second load request into a second entry of the cache memory and to set an age indicator of a metadata field of the second entry to the default age level. Other embodiments are described and claimed.
申请公布号 WO2017027111(A1) 申请公布日期 2017.02.16
申请号 WO2016US39772 申请日期 2016.06.28
申请人 INTEL CORPORATION 发明人 WANG, Ren;THEOBALD, Kevin B.;GOBRIEL, Sameh;TAI, Tsung-Yuan C.
分类号 G06F9/30;G06F12/08;G06F13/16 主分类号 G06F9/30
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