发明名称 LIQUID DISCHARGING APPARATUS, HEAD UNIT, INTEGRATED CIRCUIT DEVICE FOR CAPACITIVE LOAD DRIVING, CAPACITIVE LOAD DRIVING CIRCUIT, AND CONTROL METHOD OF LIQUID DISCHARGING APPARATUS
摘要 There is provided a driving circuit for driving a capacitive load including: a modulation portion which generates a modulation signal pulse-modulated from a source signal; a gate driver which generates an amplification control signal based on the modulation signal; a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal; a feedback circuit which sends back the driving signal to the modulation portion; a boosting circuit which supplies a voltage which has been boosted.
申请公布号 US2017043576(A1) 申请公布日期 2017.02.16
申请号 US201615336162 申请日期 2016.10.27
申请人 Seiko Epson Corporation 发明人 TAKAGI Tetsuo
分类号 B41J2/045;H03K17/687;H02M3/07 主分类号 B41J2/045
代理机构 代理人
主权项 1. A driving circuit for driving a capacitive load, comprising: a modular which generates a modulation signal pulse-modulated from a source signal; a gate driver which generates an amplification control signal based on the modulation signal; a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal of a capacitive load; a feedback circuit which sends back the driving signal to the modulator; a boosting circuit which supplies a voltage which has been boosted based on any one of a first clock signal and a second clock signal to the gate driver; and a boosting controller which controls boosting in the boosting circuit, wherein the boosting controller controls the boosting based on the second clock signal after controlling the boosting based on the first clock signal, and wherein a switching point of rising or falling of the second clock signal is synchronized with the modulation signal.
地址 Tokyo JP