SYSTEMS AND METHODS OF MEMORY BIT FLIP IDENTIFICATION FOR DEBUGGING AND POWER MANAGEMENT

摘要

Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

主权项

1. A method for debugging a memory component in a system on a chip (“SoC”), the method comprising:
monitoring one or more parameters of the SoC that are associated with bit flips; calculating a first baseline parity value for a first data block of bits queued to be written to a first bit cell array of the memory component and assigning the first baseline parity value to a parity bit associated with the first data block; writing the first data block to the first bit cell array and a buffer of the memory component; calculating a first write-side parity value from the first data block as it is stored in the buffer; comparing the first baseline parity value to the first write-side parity value; if the first baseline parity value differs from the first write-side parity value, determining that one or more bits of the first data block has experienced a bit flip while being written to the memory component; determining levels of the one or more parameters if the first baseline parity value differs from the first write-side parity value; and issuing a system halt if the first baseline parity value differs from the first write-side parity value, wherein issuing the system halt provides for determining which of the one or more parameters caused the one or more bits of the first data block to experience a bit flip.