发明名称 |
PROCESSING FIXED AND VARIABLE LENGTH NUMBERS |
摘要 |
Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands. |
申请公布号 |
US2017046128(A1) |
申请公布日期 |
2017.02.16 |
申请号 |
US201615334349 |
申请日期 |
2016.10.26 |
申请人 |
Oracle International Corporation |
发明人 |
Brooks Jeffrey S.;Olson Christopher H.;Karichkin Eugene |
分类号 |
G06F7/483;G06F7/52;G06F7/499 |
主分类号 |
G06F7/483 |
代理机构 |
|
代理人 |
|
主权项 |
1. A processor, comprising:
a floating point unit; a logic circuit coupled to the floating point unit, wherein the logic circuit is configured to:
receive an operation, a first operand and a second operand, wherein each of the first operand and the second operand include a sign and exponent block, a length block, and one or more mantissa digits;in response to a determination that the first operand and the second operand are fixed-length numbers:
process the first operand to generate a first processed operand;process the second operand to generate a second processed operand; andperform the operation using the first processed operand and the second processed operand to generate a result, wherein the result includes a sign and exponent block, and one or more mantissa digits. |
地址 |
Redwood City CA US |