发明名称 |
BINARY FREQUENCY SHIFT KEYING WITH DATA MODULATED IN DIGITAL DOMAIN AND CARRIER GENERATED FROM INTERMEDIATE FREQUENCY |
摘要 |
Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed. |
申请公布号 |
EP3130121(A1) |
申请公布日期 |
2017.02.15 |
申请号 |
EP20150776725 |
申请日期 |
2015.04.13 |
申请人 |
Texas Instruments Incorporated |
发明人 |
RAO, Aswin, Srinivasa;KUDARI, Anand;SUBBURAJ, Karthik |
分类号 |
H04L27/10;G08C19/18;H04L27/22 |
主分类号 |
H04L27/10 |
代理机构 |
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代理人 |
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地址 |
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