发明名称 |
Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors |
摘要 |
A method of forming symmetrical stress liners to maintain strain in CMOS vertical NW FETs and the resulting device are provided. Embodiments include providing a doped semiconductor layer on an upper surface of a substrate; providing a semiconductor nanowire on the doped semiconductor layer; forming a first stress layer on the doped semiconductor layer surrounding the semiconductor nanowire; forming a gate electrode layer on a portion of the first stress layer on opposite sides of the semiconductor nanowire; forming a gate dielectric layer on the first stress layer between the gate electrode layer and the semiconductor nanowire; forming an oxide layer on a remaining portion of the first stress layer; forming a second stress layer on the oxide layer, the gate dielectric layer and the gate electrode layer; and forming contacts to the gate electrode layer, the semiconductor nanowire, and the doped semiconductor layer. |
申请公布号 |
US9570552(B1) |
申请公布日期 |
2017.02.14 |
申请号 |
US201615076842 |
申请日期 |
2016.03.22 |
申请人 |
GLOBALFOUNDRIES INC. |
发明人 |
Lee Tek Po Rinus;Liu Jinping |
分类号 |
H01L29/06;H01L29/78;H01L29/66;H01L29/10;H01L21/02;H01L21/306;H01L21/3065 |
主分类号 |
H01L29/06 |
代理机构 |
Ditthavong & Steiner, P.C. |
代理人 |
Ditthavong & Steiner, P.C. |
主权项 |
1. A method comprising:
providing a doped semiconductor layer on an upper surface of a substrate; providing a semiconductor nanowire on the doped semiconductor layer; forming a first stress layer on the doped semiconductor layer surrounding the semiconductor nanowire; forming a gate electrode layer on a portion of the first stress layer on opposite sides of the semiconductor nanowire; forming a gate dielectric layer on the first stress layer between the gate electrode layer and the semiconductor nanowire; forming an oxide layer on a remaining portion of the first stress layer; forming a second stress layer on the oxide layer, the gate dielectric layer and the gate electrode layer; and forming contacts to the gate electrode layer, the semiconductor nanowire, and the doped semiconductor layer. |
地址 |
Grand Cayman KY |